The exemplary embodiments described herein relate generally to semiconductor devices and methods for the fabrication thereof and, more specifically, to semiconductor devices having PFET and NFET structures on the same substrate and methods for forming such structures.
A complementary metal oxide semiconductor device (CMOS) uses pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon-on-insulator (SOI) substrates. A MOSFET, which is used for amplifying or switching electronic signals for logic functions, has source and drain regions connected by a channel. The source region is a terminal through which current in the form of majority charge carriers enters the channel, and the drain region is a terminal through which current in the form of majority charge carriers leaves the channel. In a p-type MOSFET (hereinafter “PFET”), the majority charge carriers are holes that flow through the channel, and in an n-type MOSFET (hereinafter “NFET”), the majority charge carriers are electrons that flow through the channel. A gate overlies the channel and controls the flow of current between the source and drain regions. The channel may be defined by a thin “fin” through which the gate controls the flow of current, thereby making the PFETs and NFETs “FinFET” devices.
The material of the channel or fin generally includes silicon (Si). Particularly, with regard to some semiconductor devices in which high performance targets are desired, the channel or fin may be a high percentage (HP) SiGe material or pure germanium (Ge). However, due to high amounts of lattice mismatch, HP SiGe or Ge grown directly on silicon may be defective. When employing HP SiGe or Ge as PFETs, desirable high performance results are generally observed for {110} crystallographic planes, and when employing HP SiGe or Ge as NFETs, desirable high performance results are generally observed for {111} crystallographic planes. The use of both {110} and {111} crystallographic planes on a single FinFET or fin-type structure using HP SiGe or Ge has heretofore been problematic.